1. Field of the Invention
The present invention relates to a driver circuit for outputting transmit data the transmission line as a differential signal.
The present application claims priority of Japanese Patent Application No.2001-272778 filed on Sept. 7, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
In a trunk communications system or a like, for example, it is sometimes necessary to use a transmission line in order to interconnect functional blocks arranged separately from each other so that they can transfer data to each other.
In such a case, in order to output transmit data to the transmission line in a format of a differential signal, a driver circuit is used to match impedance of each of the blocks with that of the transmission line and also to set a signal level at a predetermined value.
FIG. 5 shows an example of the configuration of a conventional driver circuit 100, which is disclosed in Japanese Patent Application Laid-open No. 2000-22516.
As shown in FIG. 5, the conventional driver circuit 100 includes P-type MOS (Metal Oxide Semiconductor) (hereinafter referred to as PMOS) transistors 101A and 101B, N-type MOS (hereinafter referred to as NMOS) transistors 102A and 102B, and resistors 103 to 107.
In the driver circuit 100 shown in FIG. 5, the PMOS transistor 101A, the resistors 103 and 104, and the NMOS transistor 102A and the PMOS transistor 101B, the resistors 105 and 106, and the NMOS transistor 102B are connected in series between a power supply VDD and a ground (GND) respectively in such a configuration that the resistor 107 is connected between a midpoint between the resistor 103 and resistor 104, and a midpoint between the resistor 105 and resistor 106. Furthermore, the respective gates of the PMOS transistor 101A and NMOS transistor 102A are connected in parallel to an input terminal 109 and the respective gates of the PMOS transistor 101B and NMOS transistor 102B are connected in parallel to an input terminal 110, while the midpoint between the resistor 103 and resistor 104 is connected to an output terminal 111 and the midpoint between the resistor 105 and resistor 106 is connected to an output terminal 112.
In the driver circuit 100 of FIG. 5, the PMOS transistor 101A, the resistors 103 and 104, and the NMOS transistor 102A make up a first push-pull circuit, while the PMOS transistor 101B, the resistors 105 and 106, and the NMOS transistor 102B make up a second push-pull circuit.
In this configuration, suppose that transmit data including in-phase data is applied to the input terminal 109 of the first push-pull circuit and opposite-phase data obtained by inverting the transmit data is applied to the input terminal 110 of the second push-pull circuit.
When the in-phase data applied to the first input terminal 109 is LOW in level and the opposite-phase data applied to the second input terminal 110 is HIGH in level, only the PMOS transistor 101A and NMOS transistor 102B are turned ON, turning the PMOS transistor 101B and NMOS transistor 102A OFF. Furthermore, when the in-phase data input to the input terminal 109 is HIGH in level and the opposite-phase data applied to the input terminal 110 is LOW in level, only the PMOS transistor 101B and NMOS transistor 102A are turned ON, turning the PMOS transistor 101A and NMOS transistor 102B OFF.
Accordingly, at the output terminal 111 of the first push-pull circuit an opposite phase output signal with the transmit data occurs, while at the output terminal 112 of the second push-pull circuit an in-phase output signal with the transmit data occurs, so that the output signal including a differential signal synchronized with the transmit data with reference to an electric potential of a virtual midpoint C of the resistor 107 occurs between the output terminals 111 and 112.
Supposing that the resistors 103 to 106 all have an equal resistance value Ra and the resistor 107 has a resistance value 2Rs and also that the input opposite phase data and input in-phase data have an amplitude large enough to permit the PMOS transistors 101A, 101B and NMOS transistors 102A, 102B to operate in their respective saturated regions always, then internal resistances of each of the transistors 101A, 101B, 102A and 102B in operating phase is negligibly small with respect to the resistance value Ra, so that differential output impedance between the output terminals 111 and 112 when the HIGH level is output is the same as that when the LOW level is output, thus leaving the output level as being dependent on a relative magnitude relationship between the resistance value Ra and resistance value Rs.
Furthermore, the output terminals 111 and 112 of the driver circuit 100 are connected to each one wire of a two-wire type of transmission line 120 (hereinafter may referred simply to as transmission line 120), between ends of which resistors 121 and 122 are connected in series each having a resistance value RT, a midpoint of which is grounded through a capacitor 123 in an alternating-current operating phase, so that the two wires of the transmission line 120 are connected with the differential output impedance of the driver circuit 100 between the output terminals 111 and 112 on a transmission side and, on a reception side, connected with the respective resistors 121 and 122 and also to a reception circuit (not shown) having high input impedance.
Since the differential output impedance of the driver circuit 100 between the output terminals 111 and 112 is determined by a synthetic resistance value of a parallel connection of two kinds of resistors which is expressed by resistance values Ra and Rs, the resistor 107 can be used as an adjusting resistor so that the differential output impedance may be equal to characteristic impedance of the transmission line 120 and also that the resistance value RT may be equal to the characteristic impedance of the transmission line 120, thus holding both the respective transmission side and the reception side of the transmission line 120 in a matched state.
Thus, in the driver circuit 100, since the resistors (loads) 103 to 106 of the two push-pull circuits all have the same resistance value, the output impedance remains constant regardless of whether the differential output is HIGH or LOW in level, while a ratio between the resistance value Ra and resistance value RS can be changed to arbitrarily set an output amplitude to the transmission line 120 in a condition where the output impedance value is so held that the driver circuit 100 may be matched with the transmission line 120.
It is thus possible, with the driver circuit 100, to maintain a matched state with the transmission line 120 and also to decrease an output signal level of the transmission line 120 in order to prevent inductive interference against an external device (especially, other transmission lines), thus securing stable operations in a case where a number of transmission lines are established among the functional blocks.
According to the conventional driver circuit 100 shown in FIG. 5, in both the two push-pull circuits connected between the power supply VDD and the ground GND, the two resistors having the same resistance value are connected between the power-supply side PMOS transistor 101A (101B) and the ground side NMOS transistor 102A (102B) of each of these two push-pull circuits and have their midpoints each connected with a resistor in such a configuration that the two ends of this resistor are to be connected with the transmission line 120 and also that the gates of the PMOS and NMOS transistors of these two push-pull circuits are connected in parallel with each other to receive in-phase data and opposite-phase data respectively, so that it is possible to hold the output impedance constant regardless of whether the differential output is HIGH or LOW in level and so to arbitrarily set the output amplitude of the driver circuit 100 with the output impedance as holding the transmission line 120 in a matched state.
In this conventional driver circuit 100 of FIG. 5, however, voltage at the virtual midpoint C of the resistor 107 connected between the output terminals 111 and 112, that is, an offset level of the output signal is always fixed at an intermediate level between a power supply voltage and a ground voltage and so cannot be set at an arbitrary value.
Nevertheless, in a typical driver circuit, depending on the operating conditions of a reception circuit connected at reception terminals of a transmission line, an offset level of a signal transferred through the transmission line may sometimes desired to be set at a value different from half a power supply voltage, in which case, however, the conventional driver circuit 100 of FIG. 5 cannot conduct such control as to do so, which is a problem.
In view of the above, it is an object of the present invention to provide a novel driver circuit for outputting transmit data, in a format of a differential signal, to a transmission line which can set an output level at a predetermined value while matching an output impedance with characteristic impedance of the transmission line and also to set at an arbitrary value of an offset level of an output signal sent through the transmission line.
According to a first aspect of the present invention, there is provided a driver circuit for outputting to a transmission line a differential signal occurring between a first output terminal and a second output terminal as transmit data, including:
a first circuit for outputting, when in-phase data is input to a first input terminal thereof, an output signal having a logic level which corresponds to the in-phase data to the first output terminal via resistors;
a second circuit for outputting, when opposite-phase data is input to a second input terminal thereof, an output signal having a logic level which corresponds to the opposite-phase data to the second output terminal via resistors; and
an adjusting resistor connected between the first output terminal and the second output terminal,
wherein connected is a resistor between the first output terminal and a power supply or a ground, a resistor between the second output terminal and the power supply or the ground, so that an offset voltage of the differential signal can be set at a desired value.
In the foregoing first aspect, a preferable mode is one wherein each of resistors making up the driver circuit is formed on a same substrate by using a same process.
According to a second aspect of the present invention, there is provided a driver circuit including:
a first circuit in which a first switching device (for example a PMOS transistor) that is turned ON when in-phase data is input thereto at a LOW level and a first resistor are connected in series with each other between a power supply and a first output terminal and also in which a second resistor and a second switching device (for example an NMOS transistor) that is turned ON when the in-phase data is input thereto at a HIGH level are connected in series with each other between the first output terminal and a ground;
a second circuit in which a third switching device (for example a PMOS transistor) that is turned ON when opposite-phase data is input thereto at a LOW level and a third resistor are connected in series with each other between the power supply and a second output terminal and also in which a fourth resistor and a fourth switching device (for example an NMOS transistor) that is turned ON when the opposite-phase data is input thereto at a HIGH level are connected in series with each other between the second output terminal and the ground; and
a fifth resistor connected between the first output terminal and the second output terminal, wherein:
the first through fourth resistors have an equal resistance value;
a sixth resistor is connected between the first output terminal and the power supply; and
a seventh resistor is connected between the second output terminal and the power supply.
In the foregoing second aspect, a preferable mode is one wherein the sixth resistor and the seventh resistor have an equal resistance value.
Another preferable mode is one wherein a turn-ON resistance value of the first through fourth switching devices is negligible with respect to a resistance value of the first through fourth resistors respectively.
Still another preferable mode is one wherein each of switching devices making up the driver circuit is formed on a same substrate by using a same process.
According to a third aspect of the present invention, there is provided a driver circuit including:
a first circuit in which a first switching device (for example a PMOS transistor) that is turned ON when in-phase data is input thereto at a LOW level and a first resistor are connected in series with each other between a power supply and a first output terminal and also in which a second resistor and a second switching device (for example an NMOS transistor) that is turned ON when the in-phase data is input thereto at a HIGH level are connected in series with each other between the first output terminal and a ground;
a second circuit in which a third switching device (for example a PMOS transistor) that is turned ON when opposite-phase data is input thereto at a LOW level and a third resistor are connected in series with each other between the power supply and a second output terminal and also in which a fourth resistor and a fourth switching device (for example an NMOS transistor) that is turned ON when the opposite-phase data is input thereto at a HIGH level are connected in series with each other between the second output terminal and the ground; and
a fifth resistor connected between the first output terminal and the second output terminal, wherein:
the first through fourth resistors have an equal resistance value;
a sixth resistor is connected between the first output terminal and the ground; and
a seventh resistor is connected between the second output terminal and the ground.
In the foregoing third aspect, a preferable mode is one wherein the sixth resistor and the seventh resistor have an equal resistance value.
Another preferable mode is one wherein a turn-ON resistance value of the first through fourth switching devices is negligible with respect to a resistance value of the first through fourth resistors respectively.
According to a fourth aspect of the present invention, there is provided a driver circuit including:
a first circuit in which a first PMOS transistor that is turned ON when in-phase data is input thereto at a LOW level and a first resistor are connected in series with each other between a power supply and a first output terminal and also in which a second resistor and a first NMOS transistor that is turned ON when the in-phase data is input thereto at a HIGH level are connected in series with each other between the first output terminal and a ground;
a second circuit in which a second PMOS transistor that is turned ON when opposite-phase data is input thereto at a LOW level and a third resistor are connected in series with each other between the power supply and a second output terminal and also in which a fourth resistor and a second NMOS transistor that is turned ON when the opposite-phase data is input thereto at a HIGH level are connected in series with each other between the second output terminal and the ground; and
a fifth resistor connected between the first output terminal and the second output terminal, wherein:
the first through fourth resistors have an equal resistance value;
a sixth resistor is connected between the first output terminal and the power supply; and
a seventh resistor is connected between the second output terminal and the power supply.
According to a fifth aspect of the present invention, there is provided a driver circuit including:
a first circuit in which a first PMOS transistor that is turned ON when in-phase data is input thereto at a LOW level and a first resistor are connected in series with each other between a power supply and a first output terminal and also in which a second resistor and a first NMOS transistor that is turned ON when the in-phase data is input thereto at a HIGH level are connected in series with each other between the first output terminal and a ground;
a second circuit in which a second PMOS transistor that is turned ON when opposite-phase data is input thereto at a LOW level and a third resistor are connected in series with each other between the power supply and a second output terminal and also in which a fourth resistor and a second NMOS transistor that is turned ON when the opposite-phase data is input thereto at a HIGH level are connected in series with each other between the second output terminal and the ground; and
a fifth resistor connected between the first output terminal and the second output terminal, wherein:
the first through fourth resistors have an equal resistance value;
a sixth resistor is connected between the first output terminal and the ground; and
a seventh resistor is connected between the second output terminal and the ground.
With the above configurations, the output impedance remains constant regardless of whether a differential output between the output terminals is HIGH or LOW in level, so that an output amplitude to a transmission line can be set arbitrarily in a condition where an output impedance value is so held that the driver circuit may be matched with the transmission line and also an output signal offset level can be set at a value other than half of the power supply voltage. Further, even with variation of manufacture, the offset level can be held constant.